| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce deviation of a cycle from a sync node by correcting a clock even when a sync frame is not received. <P>SOLUTION: A clock synchronization circuit includes: a clock correction value calculation part 243 for calculating a correction value of the clock; a clock correction value preservation part 244 for preserving the correction value for a prescribed period; an analysis part (decoder 241) for analyzing reception signals and determining whether or not the sync frame is received; a selection circuit 242 for taking out the correction value from the clock correction value preservation part 244 when it is determined that the sync frame is not received; and a clock synchronization correction part 245 for correcting the clock using the correction value taken out in the selection circuit 242. <P>COPYRIGHT: (C)2010,JPO&INPIT |
