发明名称 Data processing apparatus, memory controlling circuit, and memory controlling method
摘要 A data processing apparatus includes a memory, an additional bit generating unit which generates an additional bit to be added to write expectation values, on a basis of the write expectation values to be written respectively to designated addresses in the memory, the additional bit and the write expectation values being supplied to the memory as write data and stored respectively in memory cells at the addresses, and a write state judging unit which reads stored data retained in the memory cells at the addresses and judges a write state of the memory cells.
申请公布号 US2010083073(A1) 申请公布日期 2010.04.01
申请号 US20090585493 申请日期 2009.09.16
申请人 NEC ELECTRONICS CORPORATION 发明人 TERAUCHI YOUJI
分类号 G06F12/00;G06F11/10;G06F12/02;H03M13/05;H03M13/09 主分类号 G06F12/00
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