发明名称 |
METHOD FOR FABRICATING DUAL POLYSILICON GATE |
摘要 |
PURPOSE: It N type impurity in the P-type poly silicon layer the counter doping and the dual poly silicon gate production method changes into N type poly silicon layer. The bowing of the metal electrode, and the tapered profile and loading of the poly silicon layer are prevented. CONSTITUTION: Provided is the substrate(11) comprised of the NMOS and PMOS. The respective N type poly silicon layer(13A) and P-type poly silicon layer(13B) are formed in the top of the substrate of PMOS and NMOS. The gate electrode metal film(15) and gate hard mask membrane are laminated on N type and P-type poly silicon layer. The gate hard mask membrane and gate electrode metal film are patterned and N type and P-type poly silicon layer expose.
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申请公布号 |
KR20100034571(A) |
申请公布日期 |
2010.04.01 |
申请号 |
KR20080093782 |
申请日期 |
2008.09.24 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
OH, SANG ROK;LEE, JAE KYUN |
分类号 |
H01L21/336;H01L21/8242;H01L27/108 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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