发明名称 SEMICONDUCTOR FLAT PACKAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME
摘要 A semiconductor flat package device capable of attaining a favorable operation and ensuring a sufficient spreading quality of solder for the lead top end is provided. A semiconductor chip 1 is encapsulated by an encapsulation resin. At first, a lead is half-blanked on the side of the top end of the lead protruding from the encapsulation region in the direction from the soldering surface to the printed circuit board, thereby forming a half-blanked region. Then, a plating layer is formed to the half-blanked region of the lead. Then, the lead is cut from the upper end of the half-blanked region formed with the plating layer in the direction from the soldering surface. The half-blanked region and the lead cut region form the top end face of the lead which forms a pseudo-planar face. Thus, a plating layer of a sufficient area is formed stably to the top end face of the lead. As a result, a solder fillet of a sufficient height is formed stably at the top end face of the lead.
申请公布号 US2010078803(A1) 申请公布日期 2010.04.01
申请号 US20090569085 申请日期 2009.09.29
申请人 NEC ELECTRONICS CORPORATION 发明人 ANDOU HIDEKO;KIYOHARA TOSHINORI
分类号 H01L23/48;H01L21/50 主分类号 H01L23/48
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