A high speed technique for options pricing in the financial industry is disclosed that can provide both high throughput and low latency. A parallel/pipelined architecture is disclosed for computing an implied volatility in connection with an option. Parallel/pipelined architectures are also disclosed for computing an option's theoretical fair price. Preferably these parallel/pipelined architectures are deployed in hardware, and more preferably reconfigurable logic such as Field Programmable Gate Arrays (FPGAs) to accelerate the options pricing operations relative to conventional software-based options pricing operations.
申请公布号
EP2168093(A1)
申请公布日期
2010.03.31
申请号
EP20080756734
申请日期
2008.06.05
申请人
EXEGY INCORPORATED
发明人
SINGLA, NAVEEN;PARSONS, SCOTT;FRANKLIN, MARK, A.;TAYLOR, DAVID, E.