发明名称
摘要 <p>In the processor (1), a first register group (16) and the address setting register (45) for a RAM (5) (local memory) represented by ASR and AMR are the object of initial setting processing when a PRST signal, which is a first reset signal, is generated. The other registers provided in the bus control section (14) are the objects of initial setting processing when a PRST signal or an HRST signal, which is a second reset signal, is generated. The second, third, and fourth register groups (41, 42, and 43) are the objects of initial setting processing when a PRST signal, an HRST signal, or an SRST signal, which is a third reset signal, is generated. When initialization is to performed, the values of the flags corresponding to each area are referred to. Only those areas whose values of the flags have been reset are initialized. <IMAGE></p>
申请公布号 JP4443067(B2) 申请公布日期 2010.03.31
申请号 JP20010129781 申请日期 2001.04.26
申请人 发明人
分类号 G06F1/24 主分类号 G06F1/24
代理机构 代理人
主权项
地址