发明名称 |
Time delay circuit and time to digital converter |
摘要 |
A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.
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申请公布号 |
US7688126(B2) |
申请公布日期 |
2010.03.30 |
申请号 |
US20090362247 |
申请日期 |
2009.01.29 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
HENZLER STEPHAN;KOEPPE SIEGMAR;LORENZ DOMINIK |
分类号 |
H03H11/26 |
主分类号 |
H03H11/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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