| 摘要 |
PURPOSE: A method for planarizing an interlayer dielectric of a semiconductor device is provided to secure a process margin of a chemical mechanical polishing process by reducing a step of the interlayer dielectric. CONSTITUTION: An interlayer dielectric(100) is deposited on a semiconductor substrate. A part of the interlayer dielectric is etched. The metal layer is deposited. A metal wiring(20) is patterned through a photo lithography process. A first interlayer dielectric is deposited. The chemical mechanical polishing process is performed. The surface of a second interlayer dielectric is planarized.
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