发明名称 VERIFICATION SUPPORT PROGRAM, VERIFICATION SUPPORT DEVICE AND VERIFICATION SUPPORT METHOD
摘要 PROBLEM TO BE SOLVED: To prevent the omission of verification of hardware including a plurality of condition branches to achieve a hardware design having no bug. SOLUTION: Upon receiving a combination circuit description 601 that is a verification target, a verification support device 100 extracts a combination of the condition branches included in the combination circuit description 601 (step S110). The verification support device generates assertion information for deciding whether all execution patterns related to the respective combinations are verified by a verification scenario 101 (step S120). COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010066787(A) 申请公布日期 2010.03.25
申请号 JP20080229674 申请日期 2008.09.08
申请人 FUJITSU LTD 发明人 MATSUDA AKIO;OISHI RYOSUKE
分类号 G06F17/50 主分类号 G06F17/50
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