摘要 |
A signal receiving circuit, which has a plurality of input channels, includes N input detecting circuits (2a-2n) that receive respective clock signals (S1-c to SN-c) included in signals (S1-SN) of N channels. Each of the input detecting circuits (2a-2n) detects a transition of an input signal of the corresponding channel, and thereafter, determines that the signal of the corresponding channel has been inputted, thereby detecting the input of the signal of the corresponding channel. When any one of the input detecting circuits (2a-2n) detects an input of a signal of the corresponding channel, a selecting circuit (3) selects and outputs the clock and data signals of the detected input signal of the corresponding channel. The selected, outputted signals are sequentially received and processed by a single phase sync circuit (4), a single serial/parallel conversion circuit (5) and so on that are shared by the N channels. Thus, only respective single input processing circuits, such as the serial/parallel conversion and so on, are used, whereby the standby currents in such input processing circuits can be reduced.
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申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;SUGIMOTO, HIROKAZU;IWATA, TORU |
发明人 |
SUGIMOTO, HIROKAZU;IWATA, TORU |