发明名称 |
Semiconductor device and method for designing the same |
摘要 |
Disclosed herewith is a semiconductor device having an SRAM cell array capable of easily evaluating the performance of transistors and the systematic fluctuation of wiring capacity/resistance. In order to form an inversion circuit required to form a ring oscillator, a test cell is disposed at each of the four corners of the SRAM cell array and the ring oscillator is operated while charging/discharging the subject bit line. Concretely, the ring oscillator is formed on a memory cell array and the ring oscillator includes test cells disposed at least at the four corners of the memory cell array respectively. At this time, a wiring that is equivalent to a bit line is used to connect the test cells to each another.
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申请公布号 |
US2010073982(A1) |
申请公布日期 |
2010.03.25 |
申请号 |
US20090458330 |
申请日期 |
2009.07.08 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
ASAYAMA SHINOBU;KOMURO TOSHIO |
分类号 |
G11C5/02;G11C5/06;G11C7/02;G11C11/00;H01S4/00;H03K3/03 |
主分类号 |
G11C5/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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