| 摘要 |
PROBLEM TO BE SOLVED: To reduce a cost required for checking a duty ratio of a clock signal. SOLUTION: A sampling time generating circuit 101 inputs a clock signal to be measured MCK, and outputs first and second sampling trigger signals to a sample-hold circuit 102 at predetermined timing before and after a time point when a half period of the clock signal to be measured MCK is elapsed from a first edge of the clock signal to be measured MCK. The sample-hold circuit 102 samples and holds the clock signal to be measured MCK in response to the first and second sampling trigger signals. The sample-hold circuit 102 configures a portion or all of scan paths, and outputs a signal held so as to verify the duty ratio from a scan output SCANOUT by a scan clock signal SCANCK. COPYRIGHT: (C)2010,JPO&INPIT
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