发明名称 DATA PROCESSING SYSTEM AND DEBUGGING METHOD
摘要 <p><P>PROBLEM TO BE SOLVED: To execute background debug processing while reproducing a low power consumption mode. <P>SOLUTION: This data processing system is provided with: a functional block operating based on a clock; a clock supply control part for controlling the supply of the clock based on an enable signal; a storage part for storing a command table in which a debug command is associated with the number of clocks necessary for the functional block to process the debug command; and a debug system part for executing the debug processing based on the input debug command. The debug system part outputs an enable signal according to the number of clocks corresponding to the input debug command by referring to the command table. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2010067038(A) 申请公布日期 2010.03.25
申请号 JP20080233247 申请日期 2008.09.11
申请人 NEC ELECTRONICS CORP 发明人 OSAKI SHINJI
分类号 G06F11/28;G06F1/06 主分类号 G06F11/28
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