Double-gate transistor structure equipped with a channel with several branches

摘要

The device has a finFET double gate transistor structure with semi-conductor bars (106-1, 106-2) that connect blocks forming source and drain regions of a transistor. Gate electrodes (152, 154) are situated on sides of the structure. An insulation spacer (140a) situated between the bars separates the electrodes. The bars have a critical dimension (Wsi), whose ratio with a critical dimension of the spacers confer a drain Induced Barrier lowering (DIBL) factor less than that of preset maximum DIBL threshold or a coupling between the electrodes greater than preset minimum coupling, to the device. An independent claim is also included for a method for forming a microelectronic double-gate transistor device.