Data processing chip with a plurality of reconfigurable cells which have a power saving mode

摘要

The unit has a programmable computer unit (EALU) for basic mathematical and logical functions. The functions and interconnections are programmed in registers, enabling processing of a number of data types without reprogramming. A state machine (SM-UNIT) controls the computer unit. Registers partially in the form of shift registers exist for each operand and the result. Result register data are fed back to an input via a multiplexer. A bus unit (BM-UNIT) enables data to be accessed from or results to be passed to a bus system with automatic synchronization of several receivers to which data are sent. Bus access is decoupled from data processing, esp. configuration and reconfiguration do not affect the data transmitter or receiver. Bus transfers are automatically controlled by a state machine (SYNC-UNIT) using handshake lines. Return messages allow the status of processing and reconfiguration to be monitored.