发明名称 MOS device and process having low resistance silicide interface using additional source/drain implant
摘要 An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm−3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.
申请公布号 US7682892(B2) 申请公布日期 2010.03.23
申请号 US20070848962 申请日期 2007.08.31
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 OBRADOVIC BORNA;EKBOTE SHASHANK;VISOKAY MARK
分类号 H01L21/8238 主分类号 H01L21/8238
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