发明名称 Hierarchical flush barrier mechanism with deadlock avoidance
摘要 A data processing system can establish or maintain data coherency by issuing a data flush operation. The data processing system can be configured as a host executing one or more independent processes using one or more lower level devices. The lower level devices can be viewed as peer devices. Any of the host or the plurality of peer devices can be configured to initiate the flush operation. A device can determine whether the initiator of a flush operation is the host or a peer device. The device can perform a flush limited to local memory, or a subset of all available memory, if a peer device initiates the flush operation.
申请公布号 US7685371(B1) 申请公布日期 2010.03.23
申请号 US20060406550 申请日期 2006.04.19
申请人 NVIDIA CORPORATION 发明人 DUNCAN SAMUEL HAMMOND;ALFIERI ROBERT A.;EDMONDSON JOHN H.;NUECHTERLEIN DAVID WILLIAM;WOODMANSEE MICHAEL A.
分类号 G06F12/00;G06F13/00;G06F13/28 主分类号 G06F12/00
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