| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a hot carrier during an exposure term by prolonging a reset state of a reset gate section during the exposure term (including part of term). Ž<P>SOLUTION: A bias generation circuit is configured using a source follower circuit of a PMOS transistor and during an exposure term or during part of the exposure term, application of a reset clock ϕRG to a reset gate section is stopped, thereby bringing the reset gate section into a reset state and reducing a hot carrier during the exposure term. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
|
