| 摘要 |
Provided is a verification system which improves the efficiency of operation verification in the development of digital LSIs. In the verification system, a verification device can communicate with a verifying apparatus through a bus interface. In the verification device, first and second partial circuits communicating with each other constitute a target for operation verification, i.e., a to-be-verified circuit. The verifying apparatus includes a software emulator which causes a CPU to execute, through a program, calculation corresponding to processing executed by the first partial circuit. A destination selection circuit is installed in a connection path between the first and second partial circuits, and is capable of switching a communication destination of the second partial circuit between the first partial circuit and the software emulator.
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