| 摘要 |
A SIMD processor architecture comprises a Linear Processor Array (LPA) (41) having a plurality of Processing Elements (PEs) (42). Each PE (42) operates on its pixel data based on a common instruction which is broadcast to all PEs (42) from a global control processor (44). To enhance the processor's capability in handling de-interlacing algorithms, there is provided a field access module (FAM) (47), an input line memory (48), and a shadow memory (49) within a working line memory (43). The input line memory (48) comprises a previous video field memory (481) for storing a first plurality of pixels from a previous video field, a current video field memory (482) for storing a plurality of pixels from a current video field and a next video field memory (483) for storing a plurality of pixels from a next video field. In a similar manner, the shadow memory (49) comprises a previous-copy video field memory (491), a current-copy video field memory (492), and a next-copy video field memory (493). The provision of the separate memories allows the processing elements to access the previous, current and next video field data simultaneously, thereby improving the efficiency of the de-interlacing operation.
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