发明名称 CLOCK TIMING CALIBRATION CIRCUIT AND CLOCK TIMING CALIBRATION METHOD FOR CALIBRATING PHASE DIFFERENCE BETWEEN DIFFERENT CLOCK SIGNALS AND RELATED ANALOG-TO-DIGITAL CONVERSION SYSTEM USING THE SAME
摘要 A clock timing calibration circuit includes a clock timing adjusting unit and a calibration control unit. The clock timing adjusting unit is for receiving an incoming reference clock signal and selectively adjusting the received reference clock signal to generate a first clock signal according to a calibration control signal. The incoming reference clock has a predetermined phase and a predetermined frequency, The calibration control unit is for checking if the phase difference between the first clock signal and a second clock signal satisfies a predetermined criterion, and for adjusting the calibration control signal when the phase difference between the first clock signal and the second clock signal does not satisfy the predetermined criterion. The predetermined criterion is to check if the phase difference falls within a specific range associated with a clock period of one of the first clock signal and the second clock signal.
申请公布号 US2010066422(A1) 申请公布日期 2010.03.18
申请号 US20090479877 申请日期 2009.06.08
申请人 TSAI JEN-CHE 发明人 TSAI JEN-CHE
分类号 H03L7/00 主分类号 H03L7/00
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