发明名称 NODE PROCESSOR FOR USE WITH LOW DENSITY PARITY CHECK DECODER USING MULTIPLE VARIABLE NODE DEGREE DISTRIBUTION CODES
摘要 A decoding system for use with different degree parity constraint nodes and highly parallel processing operates by passing messages to variable nodes based on updated states of first and second check nodes, processing messages from the variable nodes and updating states of first and second check nodes in a decoder with Z processors that operate in parallel, further processing the updated state information for the second check nodes to coordinate the states of N=Z/z sets of second check nodes, where z is the number of bits associated with the second check nodes, and repeating the process utilizing the coordinated states of the second check nodes as the updated states of the second check nodes.
申请公布号 US2010070818(A1) 申请公布日期 2010.03.18
申请号 US20080212070 申请日期 2008.09.17
申请人 ULRIKSSON BENGT A 发明人 ULRIKSSON BENGT A.
分类号 H03M13/05;G06F11/07 主分类号 H03M13/05
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