PURPOSE: An exclusive OR gate circuit is provided to improve operation stability by supplying a bias voltage to the bulk terminal of a MOS transistor. CONSTITUTION: A computation unit(10a) comprises a plurality of MOS transistors. The computation unit performs an exclusive OR operation for a first and a second input signal. A bias supply unit(20a) supplies a bias voltage to the bulk terminal of a NMOS transistor with a source terminal which is not grounded among MOS transistors of the computation unit. The computation unit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third PMOS transistor and a third NMOS transistor.
申请公布号
KR20100030121(A)
申请公布日期
2010.03.18
申请号
KR20080088914
申请日期
2008.09.09
申请人
HYNIX SEMICONDUCTOR INC.
发明人
LEE, JI WANG;KIM, YONG JU;HAN, SUNG WOO;SONG, HEE WOONG;OH, IC SU;KIM, HYUNG SOO;HWANG, TAE JIN;CHOI, HAE RANG;JANG, JAE MIN;PARK, CHANG KUN