发明名称 Programmable interconnect structures
摘要 A programmable interconnect structure for an integrated circuit comprises: a pass-gate fabricated on a substrate layer to electrically connect a first node to a second node; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer; and a programmable method to select between isolating said first and second nodes and connecting said first and second nodes. A programmable buffer structure for an integrated circuit comprises: a first and a second terminal; and a programmable pull-up and a programmable pull-down circuit coupled between said first and second terminals; and a configuration circuit including at least one memory element coupled to said pull-up and pull-down circuits; and a programmable method to select between isolating said first terminal from second terminal by deactivating said pull-up and pull-down circuits, and coupling said first terminal to second terminal by activating said pull-up and pull-down circuits. A method of forming a programmable interconnect structure for an integrated circuit comprises: fabricating one or more pass-gates on a substrate layer to electrically connect two points; and selectively fabricating either a memory circuit or a conductive pattern substantially above said pass-gates to control a portion of said pass-gates; and fabricating an interconnect and routing layer substantially above said memory circuits to connect said pass-gates and one of said memory circuits and conductive pattern.
申请公布号 US7679399(B2) 申请公布日期 2010.03.16
申请号 US20080032667 申请日期 2008.02.16
申请人 TIER LOGIC, INC. 发明人 MADURAWE RAMINDA UDAYA
分类号 H03K19/173;G06F7/38;G06F17/50;G11C5/00;H03K17/693;H03K19/177 主分类号 H03K19/173
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