发明名称 Dual redundant dynamic logic
摘要 A system and method for hardening dynamic logic against single event upset is described. A precharge circuit is hardened and then connected to two pull down networks. The two pull down networks are redundant and, under normal operating conditions, provide substantially the same outputs when receiving substantially the same inputs. The two outputs are then voted to provide an output that is hardened against single event upset. Alternatively, the two outputs may be connected to a next stage of dynamic logic circuits or other circuitry for evaluation.
申请公布号 US7679403(B2) 申请公布日期 2010.03.16
申请号 US20050269212 申请日期 2005.11.08
申请人 HONEYWELL INTERNATIONAL INC. 发明人 ERSTAD DAVID O.
分类号 H03K19/096 主分类号 H03K19/096
代理机构 代理人
主权项
地址