发明名称 Secure processor and system
摘要 A processor includes an execution unit configured to execute a program, a bus coupled to the execution unit, a local memory coupled to the bus, a DMA unit coupled to the bus, and an interface to couple the bus to an exterior, wherein the DMA unit is configured to perform a DMA transfer process in response to instruction from the execution unit, to load information by the DMA transfer process from the exterior through the interface, to decrypt the loaded information, and to write the decrypted information to the local memory by the DMA transfer process.
申请公布号 US7681044(B2) 申请公布日期 2010.03.16
申请号 US20050225180 申请日期 2005.09.14
申请人 FUJITSU MICROELECTRONICS LIMITED 发明人 GOTO SEIJI
分类号 H04L9/32;G06F11/30;H04L9/00 主分类号 H04L9/32
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