发明名称 |
VCO circuit, PLL circuit using VCO circuit, and data recording apparatus the PLL circuit |
摘要 |
A PLL circuit includes a phase comparing section, a low pass filter, a digital VCO circuit, and a frequency divider. The phase comparing section compares an inputted clock signal and a frequency-divided clock signal in phase to detect a phase difference. The low pass filter averages the phase difference outputted from the phase comparing section to output the averaged result as a frequency control input. The digital VCO circuit operates in synchronism with a reference clock signal, and generates a sync clock signal based on the frequency control input while a phase of the sync clock signal is controlled in units of predetermined resolution values. The predetermined resolution value is a 1/K (K is a natural number more than 1) of a period of the reference clock signal. The frequency divider frequency-divides the synch clock signal to generate the frequency-divided clock signal.
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申请公布号 |
US7680235(B2) |
申请公布日期 |
2010.03.16 |
申请号 |
US20040020133 |
申请日期 |
2004.12.27 |
申请人 |
NEC ELECTRONICS CORPORATION;NEC CORPORATION |
发明人 |
SANO MASAKI;KAYANUMA KINJI |
分类号 |
G11B20/10;H03D3/24;G11B20/14;H03D13/00;H03K5/00;H03L7/06;H03L7/08;H03L7/085;H03L7/087;H03L7/099;H04L7/033 |
主分类号 |
G11B20/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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