| 摘要 |
First and second serial data busses are arranged so that simultaneous transmission on the respective bus of a dominant state by one node and a recessive state by other nodes results in the dominant state being detectable on the respective bus. Transitions from a first state to a second state signal the start of a bit on the first bus. Dominant and recessive states are detected on the first and second busses at first and second predetermined times after each transition. The states represent respective dominant and recessive bits of attempted messages transmitted by nodes of the first and second busses. The dominant state is transmitted on both busses after the first and second predetermined times if the dominant state was detected on one of the first and the second busses at the first and second predetermined times.
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