发明名称 SYSTEM AND METHOD FOR REDUCING EXECUTION DIVERGENCE IN PARALLEL PROCESSING ARCHITECTURES
摘要 PURPOSE: A method for reducing execution divergence in parallel processing architectures and a system thereof are provided to decide a preferred execution type about multiple data sets among the multiple data sets. CONSTITUTION: Among multiple data sets, a data set of a preferred execution type is decided(102). The data set of a preferred execution type is allocated to a first thread(104). The first thread is processed by a parallel processing architecture. Execution commands for function of an allocated data set as an operand are applied to each thread(106).
申请公布号 KR20100029055(A) 申请公布日期 2010.03.15
申请号 KR20090083552 申请日期 2009.09.04
申请人 NVIDIA CORPORATION 发明人 AILA TIMO;LAINE SAMULI;LUEBKE DAVID;GARLAND MICHAEL;HOBEROCK JARED
分类号 G06F9/06;G06F9/38;G06F9/46 主分类号 G06F9/06
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