| 摘要 |
A circuit arrangement comprises a memory cell array (2) with at least one memory circuit (99). The memory circuit (99) comprises one non-volatile memory cell (98) inserted in a first current path (106) between a supply voltage terminal (9) and a reference potential terminal (8), and a volatile memory cell (97) inserted in a second current path (107) between the supply voltage terminal (9) and the reference potential terminal (8). The volatile memory cell (97) is coupled to the non-volatile memory cell (98) for reading the non-volatile memory cell (98).
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