发明名称 |
Scheduling control within a data processing system |
摘要 |
A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution units 24 can include error detecting circuitry 32 for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitry 6 is arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitry 32 on consecutive processing cycles. |
申请公布号 |
US2010064287(A1) |
申请公布日期 |
2010.03.11 |
申请号 |
US20090458699 |
申请日期 |
2009.07.21 |
申请人 |
ARM LIMITED |
发明人 |
BULL DAVID MICHAEL;OZER EMRE;DAS SHIDHARTHA |
分类号 |
G06F9/30;G06F9/46;G06F11/07 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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