| 摘要 |
PURPOSE: A delay locked loop circuit is provided to reduce a data output error of a semiconductor memory device by controlling the change of the delay amount of the internal clock. CONSTITUTION: A delay locked unit(301) outputs an internal clock by delaying a reference clock based on a comparison result between the reference clock and a feedback clock. The delayed amount of the reference clock is a first delay amount. The feedback clock reflects the delay modeling of a semiconductor memory device. A noise detection unit(311) controls the change of the first delay amount by an external noise after locking the internal clock. The reference clock is more delayed than the external clock of the semiconductor memory.
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