发明名称 |
MOUNTING EVALUATION STRUCTURE AND MOUNTING EVALUATION METHOD |
摘要 |
PROBLEM TO BE SOLVED: To provide a mounting evaluation structure and a mounting evaluation method, which three-dimensionally evaluate a mounting state of a chip on a substrate without depending on viewing. SOLUTION: A plurality of capacitance parts 30 including a plurality of first electrode patterns 30a arranged on a mounting face 10a of a mounting evaluation substrate 10 and a plurality of second electrode patterns 30b which confront with the first electrode patterns 30a and are installed on a lower face 20a of a mounting evaluation chip 20 are formed in the mounting evaluation structure. Capacitances in a plurality of the capacitance parts 30 are compared. The mounting state of the mounting evaluation chip 20 on the mounting evaluation substrate 10 is evaluated based on a comparison result. COPYRIGHT: (C)2010,JPO&INPIT |
申请公布号 |
JP2010056429(A) |
申请公布日期 |
2010.03.11 |
申请号 |
JP20080221949 |
申请日期 |
2008.08.29 |
申请人 |
FUKUOKA PREF GOV SANGYO KAGAKU GIJUTSU SHINKO ZAIDAN;FUKUOKA UNIV;WALTS:KK |
发明人 |
TOMOKAGE HAJIME;MORISHITA JUN;HORIUCHI HITOSHI |
分类号 |
H01L21/60 |
主分类号 |
H01L21/60 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|