CIRCUIT AND METHOD FOR OPTIMIZING MEMORY SENSE AMPLIFIER TIMING

摘要

A memory (10) has an array of memory cells (12, 16, 18), a word line driver (36), a sense amplifier (46), and a sense enable circuit (50). Each memory cell has a coupling transistor (20, 22) for coupling a storage portion (26, 28, 30, 32) to a bit line (BL). The coupling transistors have an average threshold voltage and a maximum threshold voltage. The word line driver (36) is coupled to the array and is for enabling a selected row of memory cells in the array. The sense amplifier (46) detects a state of a memory cell (12) in the selected row (WLB) in response to a sense enable signal. The sense enable circuit provides the sense enable signal at a time based on the maximum threshold voltage. This timing enables the sense amplifier (46) sufficiently late for low temperature operation while providing for faster operation at high temperature than would normally be achieved using just the average threshold voltage in providing timing of the sense enable signal.