| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a high-accuracy phase comparison circuit compatible with 1/N rate structure. <P>SOLUTION: The phase comparison circuit has N track-and-hold circuits for tracking and holding N-phase clock signals CLK in synchronization with a rising edge of input data signal DIN. Out of the N-phase clock signals output from the track-and-hold circuits, only the one whose rising edge is most synchronized with a rising edge of the input data signal DIN is selected and output as a phase difference signal. <P>COPYRIGHT: (C)2010,JPO&INPIT |
