发明名称 CHECK PATTERN AND PACKAGING EVALUATION DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a check pattern and packaging evaluation device, for performing the loading evaluation of a semiconductor chip, by easily and surely detecting a damage generated on the outside of a guard ring. SOLUTION: In a detection part 20, a plurality of electric circuits 2 are connected in parallel, or arranged in parallel with a predetermined interval, from a scribing area 6 for dicing to the outside area of the guard ring 4, toward the inner side of the semiconductor chip 5a. An output terminal 3 is connected to the detection part 20, and arranged on the outside of the guard ring 4. The condition of the damage generated on the outside area of the guard ring 4 is analyzed, based on a deviation amount of impedance owing to a break in the electric circuits 2. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010056428(A) 申请公布日期 2010.03.11
申请号 JP20080221948 申请日期 2008.08.29
申请人 FUKUOKA UNIV;WALTS:KK;FUKUOKA PREF GOV SANGYO KAGAKU GIJUTSU SHINKO ZAIDAN 发明人 TOMOKAGE HAJIME;MORISHITA JUN;HORIUCHI HITOSHI
分类号 H01L21/66;H01L21/822;H01L27/04 主分类号 H01L21/66
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