VERY LONG INSTRUCTION WORD ARCHITECTURE WITH MULTIPLE DATA QUEUES
摘要
<p>A processor may include a plurality of processing units for processing instructions, where each processing unit is associated with a discrete instruction queue. Data is read from a data queue selected by each instruction, and a sequencer manages distribution of instructions to the plurality of discrete instruction queues.</p>
申请公布号
WO2010026485(A1)
申请公布日期
2010.03.11
申请号
WO2009IB06886
申请日期
2009.09.08
申请人
BRIDGECO AG;TRAMM, MATTHIAS;STADLER, MANFRED;HITZ, CHRISTIAN