发明名称 AN INTERCONNECT IMPLEMENTING INTERNAL CONTROLS
摘要 <p>A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.</p>
申请公布号 EP2160762(A1) 申请公布日期 2010.03.10
申请号 EP20080780967 申请日期 2008.06.25
申请人 SONICS, INC.;WINGARD, DREW E.;CHOU, CHIEN-CHUN;HAMILTON, STEPHEN W.;SWARBRICK, IAN ANDREW;VAKILOTOJAR, VIDA 发明人 WINGARD, DREW E.;CHOU, CHIEN-CHUN;HAMILTON, STEPHEN W.;SWARBRICK, IAN ANDREW;VAKILOTOJAR, VIDA
分类号 H01L25/00 主分类号 H01L25/00
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