发明名称 Multiple level minimum logic network
摘要 <p>A network or interconnect structure utilizes a data flow technique that is based on timing and positioning of messages communicating through the interconnect structure. Switching control is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided. The interconnect structure operates as a "deflection" or "hot potato" system in which processing and storage overhead at each node is minimized. Elimination of a global controller and buffering at the nodes greatly reduces the amount of control and logic structures in the interconnect structure, simplifying overall control components and network interconnect components and improving speed performance of message communication. </p>
申请公布号 EP1058194(A3) 申请公布日期 2010.03.10
申请号 EP20000120146 申请日期 1996.07.19
申请人 REED, COKE S. 发明人 REED, COKE S.
分类号 G06F15/80;G06F15/173;H04L12/56;H04L12/58 主分类号 G06F15/80
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