发明名称 FUNCTIONAL DESIGN FOR UPDATING ARGUMENTS OF INTERMEDIATE SUM [S''i] OF PARALLEL ADDER IN POSITION-SIGN CODES f(+/-)
摘要 <p>FIELD: computer engineering. ^ SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic devices for carrying out summation and subtraction operations in position-sign codes. Each bit of the adder is made in form of two design-equivalent channels - for positive and conditionally negative. In one version of the invention, the ith bit of each channel contains six NOR elements. ^ EFFECT: simple functional design of the adder. ^ 9 cl, 41 dwg</p>
申请公布号 RU2362204(C9) 申请公布日期 2010.03.10
申请号 RU20070146287 申请日期 2007.12.17
申请人 PETRENKO LEV PETROVICH 发明人 PETRENKO LEV PETROVICH
分类号 G06F7/50 主分类号 G06F7/50
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