发明名称 Method and apparatus for supporting verification, and computer product
摘要 A verification support apparatus receives description data. Upon receiving the description data, the apparatus automatically generates and outputs a verification property, a verification scenario, specification data, review information, etc. In addition, the apparatus checks the description data for any element of deficiency or inconsistency before the automatic generation of the verification property. Therefore, the amount of description data can be reduced by sorting out the types of verification items and listing parameters, and various verification properties can be automatically generated by allowing a computer to read verification data. Furthermore, a design TAT can be reduced by generating the specification data. Furthermore, even a designer not familiar with a verification language such as PSL can easily execute assertion-based verification.
申请公布号 US7676777(B2) 申请公布日期 2010.03.09
申请号 US20070727623 申请日期 2007.03.27
申请人 FUJITSU MICROELECTRONICS LIMITED 发明人 KOWATARI SATOSHI;NAKAMURA YOSHIRO;SHINDO TAKAKO
分类号 G06F17/50;G01R31/28;G06F19/00 主分类号 G06F17/50
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