REGISTER SET USED IN MULTITHREADED PARALLEL PROCESSOR ARCHITECTURE

摘要

A parallel hardware-based multithreaded processor is described. The processo r includes a general purpose processor that coordinates system functions and a plurality of microengines that suppo rt multiple hardware threads or contexts (THREAD_3 ... THREAD_0). The processor maintains execution threads (THREAD_3 ... THREAD_0). The execution threads (THREAD_3 ... THREAD_0) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD_3 ... THREAD_0).