发明名称 System and method of clocking an IP core during a debugging operation
摘要 According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source.
申请公布号 US7676712(B2) 申请公布日期 2010.03.09
申请号 US20050501461 申请日期 2005.10.25
申请人 MENTOR GRAPHICS CORPORATION 发明人 BENSINGER GREG;BRAULT JEAN-MARC;MULTHAUP HANS ERICH
分类号 G01R31/28;G06F11/00;G06F11/36 主分类号 G01R31/28
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