| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a parallel/serial conversion device for performing high level signal transmission while reducing the number of signal lines. Ž<P>SOLUTION: On the basis of a clock CLK to be input to a clock terminal CLK, a parallel/serial conversion device 1 selects either the output of a shift register 2 which converts a plurality of parallel signals to be input to data input terminals SNSa to SNSh into serial signals and the output of an OR circuit 3 which performs the OR processing of a plurality of parallel signals to be input to the data input terminals SNSa to SNSh by 3S buffers 4 and 5 and a DFF 6, and outputs it to an interrupt/data terminal IRQ/DAT. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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