| 摘要 |
1,240,110. Shift registers. PLESSEY CO. Ltd. 12 Dec., 1968 [14 Dec., 1967], No. 56940/67. Heading G4C. [Also in Division H3] In a shift register each one of a chain (Fig. 3, not shown) of clocked master-slave bi-stables has cross-coupled IGFET's 3, 4, Fig. 1a, forming the master flip-flop, coupled by means such as IGFET's 9, 10 to cross-coupled IGFET's 5, 6 forming the slave flip-flop, each transistor having a load L1 to L4 and a clock pulse C being applied to the master. The loads L1 to L4 are IGFET's having their gates and drains connected to the supply earth. The clock pulse is applied to the gate electrodes of gating IGFET's 1, 2 which are respectively connected in parallel with further input gates 7, 7a and 8, 8a. The positive clock pulse renders 1 and 2 non-conducting, and one or other of master IGFET's 3, 4 is turned OFF according to whether the inputs 7, 7a are both positive or whether the inputs 8, 8a are both positive. If all gating inputs 7, 7a, 8, 8a are positive the resultant state of the master flip-flop is indeterminate and if all are zero the state is unchanged. If, for example, the master flip-flop has been set by the inputs so that IGFET 3 is ON, and 4 is OFF, the coupling IGFET 9 cannot conduct due to the positive potential at its gate, but the coupling IGFET 10 will conduct when the end of the clock pulse allows the gating IGFET 2 to conduct again. Consequently, the drain of slave flip-flop IGFET 5 goes positive and turns OFF IGFET 6, so changing the state of the slave flip -flop according to the state of the master. The outputs X, Y of the slave may be connected to the gate inputs A1, B1 (Fig. 2, not shown), so that the complete master slave arrangement acts as a J-K flip-flop responsive to J, K inputs at A, B. Set and Reset inputs may be applied to further input IGPET's C1, P1, C2, P2. |
