发明名称 CLOCK DOMAIN CHECK METHOD AND PROGRAM FOR CLOCK DOMAIN CHECK, AND RECORDING MEDIUM
摘要 PROBLEM TO BE SOLVED: To provide a technology for reducing a pseudo error. SOLUTION: A stationary signal is propagated through the circuit to be checked (103). A combination is extracted in which different asynchronous transfers occur between a transmitting side register and a receiving side register (104). From the extracted combination of asynchronous transfers, a circuit to be checked is extracted, and a synchronization circuit of a plurality of signals is excluded from the circuit to be checked (106, 107, 112). A stationary signal is propagated through the circuit to be checked, for each combination among all combinations of logic values "1" and "0" of the stationary signal (1062). It is checked whether or not there exists one asynchronous transmitting side register to which signal change can logically reach, in the combination of logic values of the stationary signal propagated (1064, 1065). Based on the result, it is determined whether or not the circuit is appropriate as a synchronization circuit for a single-signal transfer (110), thereby reducing pseudo errors. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010049385(A) 申请公布日期 2010.03.04
申请号 JP20080211458 申请日期 2008.08.20
申请人 RENESAS TECHNOLOGY CORP 发明人 SUZUKI KEIICHI;ABE MAKOTO
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址