| 摘要 |
A clock generation circuit, which includes a reference clock delay circuit including a number M of delay units connected in series, and configured to delay a reference clock by L cycles; and an oscillation circuit including a number N of delay units connected in series, and configured to generate an oscillation clock according to the following Equation, tOS = 2 N × DD = 2 N × L × tCLK M where each delay unit is configured to delay an input signal by a reference delay amount DD, tOS is a period of the oscillation clock, and tCLK is the reference clock.
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