发明名称 CASH CONTROL DEVICE AND CASH CONTROL METHOD
摘要 <p>The object is to reliably enhance processing efficiency when a pipeline process is executed on a plurality of threads. To achieve that object, when each processing unit from a cycle T processing unit (142a) to a cycle R processing unit (142d) is processing a request belonging to a stalled thread, a valid bit for the stalled thread in corresponding wait ports (143a to 143d) is set to "1". If the valid bit for any one of the threads is detected to have set to "1", a request storing unit (148) sequentially outputs requests corresponding to that valid bit to a register unit (149). Based on the valid bits, a priority determining unit (144) determines priority of the output from a selector (141). According to a select signal from the priority determining unit (144), the selector (141) outputs one of the requests.</p>
申请公布号 EP2159701(A1) 申请公布日期 2010.03.03
申请号 EP20070767197 申请日期 2007.06.19
申请人 FUJITSU LIMITED 发明人 SHIRAHIGE, YUJI
分类号 G06F12/08;G06F9/38 主分类号 G06F12/08
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