| 摘要 |
1,253,882. Multiplex pulse code signalling. TELEFONAKTIEBOLAGET L. M. ERICSSON. 31 Jan., 1969 [20 Feb., 1968], No. 5440/69. Heading H4L. An arrangement for synchronizing the distributor of a receiver in a time division multiplex P.C.M. system in which the received signal includes sync. pulses forming a first pattern for synchronizing bit distribution and superimposed thereon a second pattern for synchronizing channel distribution, comprises means responsive to loss of synchronization to control the distributer until bit synchronization is obtained and to interrupt the channel distribution until a recognizable element of the second pattern has been received after bit synchronization has been maintained over a predetermined number of channels and to set the distributer to the next channel after the one defined by said element when said interruption ceases. As described the system provides sixteen channels and eight bits per channel, the last bit of each channel being used for synchronization and consisting of alternate 0 and 1 with the exception of channels 7 and 8 each having binary 0 in this position and channels 15 and 16 each having binary 1. The input signal I, Fig. 3a, controls a generator K, Fig. 2, producing clock pulses at bit frequency, Fig. 3b, which are supplied via gate G1 to a counter BR controlling bit distributer BF having outputs B1 to B8. The output B1 is supplied via gate G2 to a counter KR controlling channel distributer KF having outputs K1 to K16, and is also supplied via gate G3 (which is inhibited by output K8 or K16 via OR gate G4) to control a bi-stable V8. The output IM of the bi-stable is supplied to a circuit D where it is compared with the incoming signal I so that if the two inputs are not equal a signal J is produced which is supplied to a gate G5 opened by output B8 of the bit distributer if an output S is provided by a bi-stable V9. The bi-stable V9 produces outputs S or S when the system is in synchronism or out of synchronism, respectively. Any output from gate G5 is supplied to a gate G6 controlled by the output R of a counter C, which is present if the count is below 3, an output from gate G6 resetting the counter to zero. The output of G6 also inhibits the gate G1 so that the distributers are stopped. The output J also inhibits a gate G7 which otherwise steps the counter C forward when B8 is energized and signals S and R are present. The output R inhibits a gate G8 receiving the output of gate G5 and controlling the bi-stable V9. Gates G9, G10 also receive the output of gate G8, gate G9 being operable in the presence of signal IM and gate G10 in the absence of that signal to reset the distributer KF to K9 or K1 respectively. Assuming that the receiver is out of synchronism and neither K8 nor K16 is energized, Fig. 3c shows the clock pulses passed by the gate G1, B1 to B8 show the corresponding outputs of the bit distributer, IM shows the output of bi-stable V8 and J shows the output of circuit D. When the first pulse in bit position 8 is received the output B5 of the distributer is energized, the distributer being stepped until bit 3 is received and B8 is energized. Under the conditions shown a pulse is present at the output of gate G6 so that gate G1 is blocked and the counter C is set to zero. When bit 5 of the incoming signal is reached the inputs to circuit D become equal and signal J ceases so that counter C is stepped forward via gate G7 and the distributor commences stepping again and bi-stable V 8 changes state when B1 is energized. When B8 is reached again, bit 5 is being received so that gate G1 is blocked and counter C set to zero. The next pulse received is a binary 1 so that the distributer starts stepping again, the counter C steps forward and V 8 changes its state. When B8 becomes energized for the third time the next two pulses (6 and 7) received are binary ones and gate G1 is blocked. The third pulse is binary 0 (pulse 8) and stepping restarts with the bit distributer set to its correct position. if the counter C is now stepped forward three times without the occurrence of a zero-setting pulse, the output signal R of the counter ceases and gates G6, G7 are blocked and when the last bit of channel 8 or 16 is received an output will be provided by gate G5 which is supplied via gate G8 to operate bi-stable V9 to produce output S and to reset the distributer KR via gate G9 or G10 so that the receiver is synchronized. |
