发明名称 INFORMATION PROCESSOR AND CACHE CONTROL METHOD
摘要 <p>[Object] It is an object of an information processing apparatus according to the present invention to allow detection of a serial-access pattern in accesses even when the access order is reversed across a registration block boundary in a cache memory or the access addresses are discrete. [Solving Means] An information processing apparatus according to an embodiment of the invention includes a processor, a first storage portion that stores data, a second storage portion that fetches data to be processed in the processor from the first storage portion, an entry holding portion that manages data access histories held in blocks in the second storage portion, and a control portion that updates the access history to the current block held in the entry holding portion when the access destination by the processor is changed from the current block to the most lately accessed block.</p>
申请公布号 EP2159699(A1) 申请公布日期 2010.03.03
申请号 EP20070767160 申请日期 2007.06.19
申请人 FUJITSU LIMITED 发明人 OKAWARA, HIDEKI;YAMAZAKI, IWAO
分类号 G06F12/08 主分类号 G06F12/08
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